1. Field of the Invention
This invention relates to electrically erasable programmable read-only memories (EEPROMs) and in particular to structures for erasing EEPROMs.
2. Description of the Prior Art
A number of types of EEPROMs are available on the market. One type of EEPROM is programmed and erased using an electron tunneling mechanism. Such an EEPROM is discussed by Johnson et al. in a paper entitled "A 16 Kb Electrically Erasable Nonvolatile Memory", published at the IEEE International Solid-State Circuits Conference. On Feb. 14, 1980, pp. 152-153, 271, incorporated herein by reference. FIG. 1 illustrates the Johnson transistor in cross section. In the Johnson EEPROM 10, during programming, electrons tunnel from a drain region 12, through a tunneling oxide region 14, and onto a floating gate 16. During erase, electrons tunnel from floating gate 16 through the tunneling oxide 14 to drain 12. Unfortunately, the Johnson EEPROM has a number of drawbacks.
To ensure proper operation of EEPROMs which use tunneling for programming and erasing, tunneling oxide 14 must generally be formed to a thickness less than or equal to about 100 .ANG.. This is because it is difficult to generate a large voltage across the tunneling oxide for both programming and erasing since the optimum capacitive coupling between the floating gate and the substrate is different for programming by tunneling as opposed to erasing by tunneling. This problem is exacerbated since by making tunneling oxide 14 thin, the capacitive coupling between drain region 12 and floating gate 16 is increased. This increase in drain-floating gate capacitive coupling makes it more difficult to program or erase the EEPROM of FIG. 1. Accordingly, to generate an electric field of appropriate magnitude for both programming and erasing, the tunneling oxide thickness is minimized. Unfortunately, it is difficult to form a tunneling oxide layer which has a thickness on the order of 100 .ANG. due to the high defect density associated with such a thin oxide layer.
Another problem with the Johnson device is that the capacitive coupling between floating gate 16 and the other structures in the transistor must be optimized for both tunneling from drain 12 to floating gate 16 and from floating gate 16 to drain 12. Such optimization requires a large cell size.
Another problem is that after electrical erase, floating gate 16 is typically positively charged so that an N type inversion region may form under floating gate 16 extending from source 17 to drain 12 independently of the voltage at the control gate 18. Because of this, the EEPROM may remain on perpetually. Thus, Johnson must couple an extra select transistor (not shown in FIG. 1) between each EEPROM cell transistor and its corresponding bit line (see FIG. 3 of the Johnson reference) so that it is possible to individually sense the state of each transistor coupled to the bit line. This extra select transistor makes each transistor cell large and thus expensive.
Another problem is that because the programming and erase voltages are applied to control gate 18 and drain 12, respectively, the CMOS transistors within the decode logic of the EEPROM (used to apply read and erase voltages to selected drains and control gates with the EEPROM array) must be able to withstand high voltages without breaking down. Thus, the decode logic must be constructed using transistors having thick gate insulation and long channel regions. Such transistors tend to be large and slow.
Another type of EEPROM is programmed using a hot electron injection mechanism, i.e. the same mechanism typically used to program conventional EPROMs, but is erased by an electron tunneling mechanism, e.g. between the floating gate and source. See, for example, Kynett et al., "An In-System Reprogrammable 256 k CMOS Flash Memory", IEEE International Solid-State Circuits Conference, Feb. 18, 1988, pp. 132-133, 330. FIG. 2 illustrates an EEPROM 30 programmed by hot electron injection but erased by tunneling. EEPROM 30 has a cross section appearance similar to the Johnson EEPROM except that N+ source 33 is formed within an N- region 35 to mitigate the problem of band-to-band tunneling (discussed below) Also, the insulation between drain 32 and floating gate 34 is thicker than 100 .ANG., and is thus easier to build. In addition, it is easier to optimize the capacitive coupling between floating gate 34 and the other structures in the transistor for hot electron injection programming and tunneling erase than for a transistor using tunneling for both programming and erase. However, EEPROM 30 has a number of the drawbacks exhibited by the Johnson transistor. For example, because the EEPROM decode logic is exposed to the erase voltage, the decode logic must comprise transistors which are capable of handling large voltages. Such transistors are generally large and slow. Also, during electrical erase, it is possible to remove either too few or too many electrons from floating gate 34. If too many electrons are removed from floating gate 34, the floating gate will have a net positive charge, and therefore, the transistor may remain on regardless of the voltage applied to control gate 36. If too few electrons are removed from the floating gate during erase, the transistor may thereafter remain off regardless of the electrical potential at control gate 36. Thus, the amount of charge left on floating gate 34 must be carefully controlled, and it is difficult to attain such control over an EEPROM array including several hundred thousand transistors.
Another problem with EEPROM 30 is that during electrical erase, it is necessary to apply a large voltage to source 33 while connecting control gate 36 to ground in order to generate a large electric field across tunneling oxide 38. Unfortunately, this causes the junction between source 33 and P type substrate 42 to break down due to a mechanism known as "band-to-band tunneling." (Band-to-band tunneling occurs when the electric field generated under erase conditions causes a P+ inversion region, known as a deep depletion region, to form at the edge of the source. Current carriers tunnel from the source to the deep depletion region and are injected into the channel. This mechanism is described in greater detail by A. Kolodney et al. in the article "Analysis and Modeling of Floating Gate E.sup.2 PROM Cells", IEEE Transactions on Electron Devices, Vol ED-33, No. 6, pages 835 to 844, published in June 1986, incorporated herein by reference.) Because the source-substrate junction breaks down, a large current flows through source 33 during erase, and therefore, the voltage supply coupled to source 33 must be capable of providing a large amount of current (typically 2 to 20 mA for a 256 K bit EEPROM) Because of this, the erase voltage applied to source 33 cannot be generated on chip using a voltage multiplier circuit, but must instead be generated off chip, using a separate power supply. Such power supplies are typically expensive to incorporate in a system environment.
When the source-substrate junction breaks down, holes from the deep depletion region can also be injected into and entrapped in tunneling oxide 38. The presence of these entrapped holes alters the tunneling characteristics of tunneling oxide 38. Different transistors within the EEPROM cell array may have varying numbers of holes entrapped within the tunneling oxide and this variation in the number of holes causes variation in the tunneling characteristics in the array of transistors.
The entrapped holes can also increase the electric field in portions of tunneling oxide 38 under erase conditions This increased electric field can stress and degrade tunneling oxide 38 so that it no longer effectively insulates floating gate 34 from drain 32 and source 33.
As mentioned above, N+ source region 33 is formed within an N- region 35, which mitigates, but does not prevent, the problem of band-to-band tunneling.
Another type of EEPROM cell transistor is transistor 50 illustrated in FIG. 3. Transistor 50 employs a split-gate EEPROM structure, i.e. floating gate 52 covers a first portion 53 of the channel region between N+ source 54 and N+drain 56, but not a second portion 57 of the channel region. Control gate 58 covers both floating gate 52 and second portion 57 of the channel region between source 54 and drain 56. Transistor 50 is erased by grounding control gate 58 and applying a large voltage (typically 15 to 20 volts) to drain region 56. Because of the split gate architecture, even if a positive charge remains on floating gate 52 after electrical erase, a conductive channel extending from drain 56 to source 54 will not form unless a high voltage (e.g. greater than 1.0 volts) is applied to control gate 58, and thus transistor 50 will not perpetually remain on. However, transistor 50 still has some of the drawbacks which affect transistor 30 (FIG. 5). For example, the decode logic coupled to drain 56 must be capable of handling large voltages. Also, during electrical erase, the high voltage applied to drain 56 causes junction 60 between drain 56 and P type substrate 62 to break down due to the above-mentioned band-to-band tunneling mechanism. Because of this, it is necessary to couple an external voltage source capable of providing a large amount of current to drain 56 during electrical erase. The breakdown of junction 60 also causes the above-mentioned problem of hole entrapment in silicon dioxide 64 between floating gate 52 and drain 56.
EEPROMs such as EEPROM 50 are described in more detail by Samachisa et al. in "A 128 K Flash EEPROM Using Double Polysilicon Technology". published at the IEEE Solid State Circuits Conference on Feb. 25, 1987, pp. 76-77, 345.
It is also known to provide a dedicated polysilicon erase gate in an EEPROM, e.g., as described in U.S. Pat. No. 4,531,203, issued to Masuoka et al., incorporated herein by reference. In such a structure, the floating gate is erased by causing electrons to tunnel from the floating gate to the polysilicon erase gate. Masuoka's structure is constructed by depositing and patterning three polysilicon layers. The first layer is used to form the erase gate, the second layer is used to form the floating gate, and the third layer is used to form the control gate. Thus, the process used to form this EEPROM is complicated and expensive.
Another type of EEPROM including a dedicated erase gate is discussed in U.S. Pat. No. 4,561,004, issued to Kuo et al., incorporated herein by reference. FIGS. 4a and 4b are simplified illustrations in plan view and cross section, respectively, of an array of transistors constructed in accordance with Kuo et al's patent. (FIG. 4b is the cross section along lines A--A of FIG. 4a.) A typical transistor within Kuo's array is transistor 70, which includes a source 72, a drain 74, a floating gate 76, a control gate 78, and an erase gate 80.
Kuo utilizes a split gate architecture, i.e. his floating gate 76 covers a first portion 84 of his channel region but not a second portion 86. Control gate 78 covers floating gate 76 and second portion 86 of the channel. Thus, even if floating gate 76 is positively charged after electrical erase, an N type inversion region forming under floating gate 76 will not extend from drain 74 to source 72, and thus transistor 70 will not remain turned on perpetually (Although floating gate 76 includes a portion 88 which extends all the way from drain 74 to source 72, portion 88 of floating gate 76 extends over the field oxide region of transistor 70, and thus an N type inversion region does not form under portion 88 of floating gate 76.
Kuo forms his source and drain regions 72 and 74 prior to forming floating gate 76. Unfortunately, if floating gate 76 is misaligned relative to the channel region, the length L of portion 84 of the channel underneath floating gate 76 can vary. If length L is nominally 1.mu.m, under presently practical alignment tolerances, the actual value of length L will be 1.mu.m.+-.0.6 .mu.m. This results in a very wide variation in performance between wafers processed in different lots. (The reasons for this variation are described in U.S. Pat. No. 4,639,893, issued to Eitan and incorporated herein by reference.)